0000008a <__bad_interrupt>: 8a: 0c 94 00 00 jmp 0x0 <__heap_end> 0000008e <__vector_11>: REFERNENCE ASSEMBLER OUTPUT WHEN MODIFYING THIS PWM FUNCTION gcc -O1 **********************************************************/ SIGNAL (SIG_OVERFLOW0) { 8e: 1f 92 push r1 90: 0f 92 push r0 92: 0f b6 in r0, 0x3f ; 63 94: 0f 92 push r0 96: 11 24 eor r1, r1 98: 8f 93 push r24 9a: 9f 93 push r25 if (++pwmcount == 0){ 9c: 80 91 74 00 lds r24, 0x0074 a0: 98 2f mov r25, r24 a2: 9f 5f subi r25, 0xFF ; 255 a4: 90 93 74 00 sts 0x0074, r25 a8: 99 23 and r25, r25 aa: a1 f4 brne .+40 ; 0xd4 <__vector_11+0x46> p0 = pwm0; p1 = pwm1; p2 = pwm2; p3 = pwm3; ac: 80 91 76 00 lds r24, 0x0076 b0: 80 93 60 00 sts 0x0060, r24 b4: 80 91 61 00 lds r24, 0x0061 b8: 80 93 75 00 sts 0x0075, r24 bc: 80 91 62 00 lds r24, 0x0062 c0: 80 93 63 00 sts 0x0063, r24 c4: 80 91 77 00 lds r24, 0x0077 c8: 80 93 78 00 sts 0x0078, r24 SetBit(PWM0BIT, PWM0PORT); cc: c0 9a sbi 0x18, 0 ; 24 SetBit(PWM1BIT, PWM1PORT); ce: c1 9a sbi 0x18, 1 ; 24 SetBit(PWM2BIT, PWM2PORT); d0: c2 9a sbi 0x18, 2 ; 24 SetBit(PWM3BIT, PWM3PORT); d2: c3 9a sbi 0x18, 3 ; 24 }; if ((p0 ^ pwmcount) == 0) { ClearBit(PWM0BIT, PWM0PORT); } d4: 80 91 60 00 lds r24, 0x0060 d8: 98 17 cp r25, r24 da: 09 f4 brne .+2 ; 0xde <__vector_11+0x50> dc: c0 98 cbi 0x18, 0 ; 24 if ((p1 ^ pwmcount) == 0) { ClearBit(PWM1BIT, PWM1PORT); } de: 80 91 75 00 lds r24, 0x0075 e2: 98 17 cp r25, r24 e4: 09 f4 brne .+2 ; 0xe8 <__vector_11+0x5a> e6: c1 98 cbi 0x18, 1 ; 24 if ((p2 ^ pwmcount) == 0) { ClearBit(PWM2BIT, PWM2PORT); } e8: 80 91 63 00 lds r24, 0x0063 ec: 98 17 cp r25, r24 ee: 09 f4 brne .+2 ; 0xf2 <__vector_11+0x64> f0: c2 98 cbi 0x18, 2 ; 24 if ((p3 ^ pwmcount) == 0) { ClearBit(PWM3BIT, PWM3PORT); } f2: 80 91 78 00 lds r24, 0x0078 f6: 98 17 cp r25, r24 f8: 09 f4 brne .+2 ; 0xfc <__vector_11+0x6e> fa: c3 98 cbi 0x18, 3 ; 24 fc: 9f 91 pop r25 fe: 8f 91 pop r24 100: 0f 90 pop r0 102: 0f be out 0x3f, r0 ; 63 104: 0f 90 pop r0 106: 1f 90 pop r1 108: 18 95 reti 0000010a : } void timerInit(void) { // set prescaler to /1 TCCR0 = (0 << FOC0 | 0 << WGM00 |0 << COM01 |0 << COM00 |0 << WGM01 |0 << CS02 |0 << CS01 |1 << CS00); 10a: 81 e0 ldi r24, 0x01 ; 1 10c: 83 bf out 0x33, r24 ; 51 // set interrupt mask register TIMSK |= (1<: } void AnalogInit (void) { int i; // Activate ADC with Prescaler ADCSRA = 1 << ADEN | 116: 8c ec ldi r24, 0xCC ; 204 118: 86 b9 out 0x06, r24 ; 6 11a: 80 e0 ldi r24, 0x00 ; 0 11c: 90 e0 ldi r25, 0x00 ; 0 11e: 24 e6 ldi r18, 0x64 ; 100 120: 30 e0 ldi r19, 0x00 ; 0 1 << ADSC | /* start a converstion, irq will take from here */ 0 << ADATE | 0 << ADIF | 1 << ADIE | /* enable interrupt */ 1 << ADPS2 | 0 << ADPS1 | 0 << ADPS0 ; for (i = 0; i < 8; AdcValues[i++] = 0); 122: fc 01 movw r30, r24 124: ee 0f add r30, r30 126: ff 1f adc r31, r31 128: e2 0f add r30, r18 12a: f3 1f adc r31, r19 12c: 11 82 std Z+1, r1 ; 0x01 12e: 10 82 st Z, r1 130: 01 96 adiw r24, 0x01 ; 1 132: 88 30 cpi r24, 0x08 ; 8 134: 91 05 cpc r25, r1 136: a9 f7 brne .-22 ; 0x122 138: 08 95 ret 0000013a

: 13a: cf e5 ldi r28, 0x5F ; 95 13c: d8 e0 ldi r29, 0x08 ; 8 13e: de bf out 0x3e, r29 ; 62 140: cd bf out 0x3d, r28 ; 61 142: 1a ba out 0x1a, r1 ; 26 144: 8f ef ldi r24, 0xFF ; 255 146: 87 bb out 0x17, r24 ; 23 148: 14 ba out 0x14, r1 ; 20 14a: 11 ba out 0x11, r1 ; 17 14c: 10 92 76 00 sts 0x0076, r1 150: 10 92 61 00 sts 0x0061, r1 154: 10 92 62 00 sts 0x0062, r1 158: 10 92 77 00 sts 0x0077, r1 15c: 0e 94 8b 00 call 0x116 160: 0e 94 85 00 call 0x10a 164: 78 94 sei 166: 20 91 64 00 lds r18, 0x0064 16a: 30 91 65 00 lds r19, 0x0065 16e: 80 91 66 00 lds r24, 0x0066 172: 90 91 67 00 lds r25, 0x0067 176: 28 1b sub r18, r24 178: 39 0b sbc r19, r25 17a: c9 01 movw r24, r18 17c: 22 f4 brpl .+8 ; 0x186 17e: 88 27 eor r24, r24 180: 99 27 eor r25, r25 182: 82 1b sub r24, r18 184: 93 0b sbc r25, r19 186: 8f 3f cpi r24, 0xFF ; 255 188: 91 05 cpc r25, r1 18a: 19 f0 breq .+6 ; 0x192 18c: 14 f0 brlt .+4 ; 0x192 18e: 8f ef ldi r24, 0xFF ; 255 190: 90 e0 ldi r25, 0x00 ; 0 192: 80 93 76 00 sts 0x0076, r24 196: 12 16 cp r1, r18 198: 13 06 cpc r1, r19 19a: 14 f4 brge .+4 ; 0x1a0 19c: c4 9a sbi 0x18, 4 ; 24 19e: 01 c0 rjmp .+2 ; 0x1a2 1a0: c4 98 cbi 0x18, 4 ; 24 1a2: 20 91 68 00 lds r18, 0x0068 1a6: 30 91 69 00 lds r19, 0x0069 1aa: 80 91 6a 00 lds r24, 0x006A 1ae: 90 91 6b 00 lds r25, 0x006B 1b2: 28 1b sub r18, r24 1b4: 39 0b sbc r19, r25 1b6: c9 01 movw r24, r18 1b8: 22 f4 brpl .+8 ; 0x1c2 1ba: 88 27 eor r24, r24 1bc: 99 27 eor r25, r25 1be: 82 1b sub r24, r18 1c0: 93 0b sbc r25, r19 1c2: 8f 3f cpi r24, 0xFF ; 255 1c4: 91 05 cpc r25, r1 1c6: 19 f0 breq .+6 ; 0x1ce 1c8: 14 f0 brlt .+4 ; 0x1ce 1ca: 8f ef ldi r24, 0xFF ; 255 1cc: 90 e0 ldi r25, 0x00 ; 0 1ce: 80 93 61 00 sts 0x0061, r24 1d2: 12 16 cp r1, r18 1d4: 13 06 cpc r1, r19 1d6: 14 f4 brge .+4 ; 0x1dc 1d8: c5 9a sbi 0x18, 5 ; 24 1da: 01 c0 rjmp .+2 ; 0x1de 1dc: c5 98 cbi 0x18, 5 ; 24 1de: 20 91 6c 00 lds r18, 0x006C 1e2: 30 91 6d 00 lds r19, 0x006D 1e6: 80 91 6e 00 lds r24, 0x006E 1ea: 90 91 6f 00 lds r25, 0x006F 1ee: 28 1b sub r18, r24 1f0: 39 0b sbc r19, r25 1f2: c9 01 movw r24, r18 1f4: 22 f4 brpl .+8 ; 0x1fe 1f6: 88 27 eor r24, r24 1f8: 99 27 eor r25, r25 1fa: 82 1b sub r24, r18 1fc: 93 0b sbc r25, r19 1fe: 8f 3f cpi r24, 0xFF ; 255 200: 91 05 cpc r25, r1 202: 19 f0 breq .+6 ; 0x20a 204: 14 f0 brlt .+4 ; 0x20a 206: 8f ef ldi r24, 0xFF ; 255 208: 90 e0 ldi r25, 0x00 ; 0 20a: 80 93 62 00 sts 0x0062, r24 20e: 12 16 cp r1, r18 210: 13 06 cpc r1, r19 212: 14 f4 brge .+4 ; 0x218 214: c6 9a sbi 0x18, 6 ; 24 216: 01 c0 rjmp .+2 ; 0x21a 218: c6 98 cbi 0x18, 6 ; 24 21a: 20 91 70 00 lds r18, 0x0070 21e: 30 91 71 00 lds r19, 0x0071 222: 80 91 72 00 lds r24, 0x0072 226: 90 91 73 00 lds r25, 0x0073 22a: 28 1b sub r18, r24 22c: 39 0b sbc r19, r25 22e: c9 01 movw r24, r18 230: 22 f4 brpl .+8 ; 0x23a 232: 88 27 eor r24, r24 234: 99 27 eor r25, r25 236: 82 1b sub r24, r18 238: 93 0b sbc r25, r19 23a: 8f 3f cpi r24, 0xFF ; 255 23c: 91 05 cpc r25, r1 23e: 19 f0 breq .+6 ; 0x246 240: 14 f0 brlt .+4 ; 0x246 242: 8f ef ldi r24, 0xFF ; 255 244: 90 e0 ldi r25, 0x00 ; 0 246: 80 93 77 00 sts 0x0077, r24 24a: 12 16 cp r1, r18 24c: 13 06 cpc r1, r19 24e: 14 f4 brge .+4 ; 0x254 250: c7 9a sbi 0x18, 7 ; 24 252: 89 cf rjmp .-238 ; 0x166 254: c7 98 cbi 0x18, 7 ; 24 256: 87 cf rjmp .-242 ; 0x166 00000258 : } int Analog (int n) { return AdcValues[n & 7]; 258: fc 01 movw r30, r24 25a: e7 70 andi r30, 0x07 ; 7 25c: f0 70 andi r31, 0x00 ; 0 25e: ee 0f add r30, r30 260: ff 1f adc r31, r31 262: ec 59 subi r30, 0x9C ; 156 264: ff 4f sbci r31, 0xFF ; 255 266: 80 81 ld r24, Z 268: 91 81 ldd r25, Z+1 ; 0x01 26a: 08 95 ret 0000026c <__vector_16>: } SIGNAL(SIG_ADC) { 26c: 1f 92 push r1 26e: 0f 92 push r0 270: 0f b6 in r0, 0x3f ; 63 272: 0f 92 push r0 274: 11 24 eor r1, r1 276: 2f 93 push r18 278: 3f 93 push r19 27a: 8f 93 push r24 27c: 9f 93 push r25 27e: ef 93 push r30 280: ff 93 push r31 int i; i = ADMUX & 7; // what channel we on? 282: 87 b1 in r24, 0x07 ; 7 284: 99 27 eor r25, r25 286: 87 70 andi r24, 0x07 ; 7 288: 90 70 andi r25, 0x00 ; 0 AdcValues[i] = ADC; // save value 28a: 24 b1 in r18, 0x04 ; 4 28c: 35 b1 in r19, 0x05 ; 5 28e: fc 01 movw r30, r24 290: ee 0f add r30, r30 292: ff 1f adc r31, r31 294: ec 59 subi r30, 0x9C ; 156 296: ff 4f sbci r31, 0xFF ; 255 298: 31 83 std Z+1, r19 ; 0x01 29a: 20 83 st Z, r18 i++; // next value ADMUX = i & 7; // select channel 29c: 01 96 adiw r24, 0x01 ; 1 29e: 87 70 andi r24, 0x07 ; 7 2a0: 87 b9 out 0x07, r24 ; 7 ADCSRA |= _BV(ADSC); // start next conversion 2a2: 36 9a sbi 0x06, 6 ; 6 2a4: ff 91 pop r31 2a6: ef 91 pop r30 2a8: 9f 91 pop r25 2aa: 8f 91 pop r24 2ac: 3f 91 pop r19 2ae: 2f 91 pop r18 2b0: 0f 90 pop r0 2b2: 0f be out 0x3f, r0 ; 63 2b4: 0f 90 pop r0 2b6: 1f 90 pop r1 2b8: 18 95 reti