
main.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         0000026c  00000000  00000000  00000094  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data         00000010  00800060  0000026c  00000300  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bss          00000003  00800070  00800070  00000310  2**0
                  ALLOC
  3 .noinit       00000000  00800073  00800073  00000310  2**0
                  CONTENTS
  4 .eeprom       00000000  00810000  00810000  00000310  2**0
                  CONTENTS
  5 .stab         0000099c  00000000  00000000  00000310  2**2
                  CONTENTS, READONLY, DEBUGGING
  6 .stabstr      00000957  00000000  00000000  00000cac  2**0
                  CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 2a 00 	jmp	0x54
   4:	0c 94 ee 00 	jmp	0x1dc
   8:	0c 94 12 01 	jmp	0x224
   c:	0c 94 45 00 	jmp	0x8a
  10:	0c 94 45 00 	jmp	0x8a
  14:	0c 94 45 00 	jmp	0x8a
  18:	0c 94 45 00 	jmp	0x8a
  1c:	0c 94 45 00 	jmp	0x8a
  20:	0c 94 45 00 	jmp	0x8a
  24:	0c 94 45 00 	jmp	0x8a
  28:	0c 94 45 00 	jmp	0x8a
  2c:	0c 94 45 00 	jmp	0x8a
  30:	0c 94 45 00 	jmp	0x8a
  34:	0c 94 45 00 	jmp	0x8a
  38:	0c 94 45 00 	jmp	0x8a
  3c:	0c 94 45 00 	jmp	0x8a
  40:	0c 94 45 00 	jmp	0x8a
  44:	0c 94 45 00 	jmp	0x8a
  48:	0c 94 45 00 	jmp	0x8a
  4c:	0c 94 45 00 	jmp	0x8a
  50:	0c 94 45 00 	jmp	0x8a

00000054 <__ctors_end>:
  54:	11 24       	eor	r1, r1
  56:	1f be       	out	0x3f, r1	; 63
  58:	cf e5       	ldi	r28, 0x5F	; 95
  5a:	d8 e0       	ldi	r29, 0x08	; 8
  5c:	de bf       	out	0x3e, r29	; 62
  5e:	cd bf       	out	0x3d, r28	; 61

00000060 <__do_copy_data>:
  60:	10 e0       	ldi	r17, 0x00	; 0
  62:	a0 e6       	ldi	r26, 0x60	; 96
  64:	b0 e0       	ldi	r27, 0x00	; 0
  66:	ec e6       	ldi	r30, 0x6C	; 108
  68:	f2 e0       	ldi	r31, 0x02	; 2
  6a:	02 c0       	rjmp	.+4      	; 0x70

0000006c <.do_copy_data_loop>:
  6c:	05 90       	lpm	r0, Z+
  6e:	0d 92       	st	X+, r0

00000070 <.do_copy_data_start>:
  70:	a0 37       	cpi	r26, 0x70	; 112
  72:	b1 07       	cpc	r27, r17
  74:	d9 f7       	brne	.-10     	; 0x6c

00000076 <__do_clear_bss>:
  76:	10 e0       	ldi	r17, 0x00	; 0
  78:	a0 e7       	ldi	r26, 0x70	; 112
  7a:	b0 e0       	ldi	r27, 0x00	; 0
  7c:	01 c0       	rjmp	.+2      	; 0x80

0000007e <.do_clear_bss_loop>:
  7e:	1d 92       	st	X+, r1

00000080 <.do_clear_bss_start>:
  80:	a3 37       	cpi	r26, 0x73	; 115
  82:	b1 07       	cpc	r27, r17
  84:	e1 f7       	brne	.-8      	; 0x7e
  86:	0c 94 82 00 	jmp	0x104

0000008a <__bad_interrupt>:
  8a:	0c 94 00 00 	jmp	0x0

0000008e <pwm_init>:
}

void pwm_init() {
  // clear pwm levels
  OCR0 = 0; 
  8e:	1c be       	out	0x3c, r1	; 60
  OCR2 = 0;
  90:	13 bc       	out	0x23, r1	; 35
  
  // set up WGM, clock, and mode for timer 0
  TCCR0 = 0 << FOC0  | 
  92:	8d e6       	ldi	r24, 0x6D	; 109
  94:	83 bf       	out	0x33, r24	; 51
          1 << WGM00 | /* fast pwm */
          1 << COM01 | /* inverted */
          0 << COM00 | /*   this bit 1 for inverted, 0 for normal  */
          1 << WGM01 | /* fast pwm */
          1 << CS02  | /* prescale by 1024 */
          0 << CS01  |
          1 << CS00  ;
  
  // set up WGM, clock, and mode for timer 2
  TCCR2 = 0 << FOC2  | 
  96:	85 bd       	out	0x25, r24	; 37
  98:	08 95       	ret

0000009a <setupEncoder>:
          1 << WGM20 |
          1 << COM21 |
          0 << COM20 | /*   this bit 1 for inverted, 0 for normal  */
          1 << WGM21 |
          1 << CS22  |
          0 << CS21  |
          1 << CS20  ;
  
 }

void setupEncoder() {
	// clear position
	position = 0; 
  9a:	10 92 72 00 	sts	0x0072, r1
  9e:	10 92 71 00 	sts	0x0071, r1
 
	// we need to set up int0 and int1 to 
	// trigger interrupts on both edges
	MCUCR = (1<<ISC10) | (1<<ISC00);
  a2:	85 e0       	ldi	r24, 0x05	; 5
  a4:	85 bf       	out	0x35, r24	; 53
 
	// then enable them.
	GICR  = (1<<INT0) | (1<<INT1);
  a6:	80 ec       	ldi	r24, 0xC0	; 192
  a8:	8b bf       	out	0x3b, r24	; 59
  aa:	08 95       	ret

000000ac <SetDir>:
  ac:	88 23       	and	r24, r24
  ae:	21 f4       	brne	.+8      	; 0xb8
  b0:	c0 9a       	sbi	0x18, 0	; 24
  b2:	8d e6       	ldi	r24, 0x6D	; 109
  b4:	83 bf       	out	0x33, r24	; 51
  b6:	08 95       	ret
  b8:	c0 98       	cbi	0x18, 0	; 24
  ba:	8d e7       	ldi	r24, 0x7D	; 125
  bc:	83 bf       	out	0x33, r24	; 51
  be:	08 95       	ret
  c0:	08 95       	ret

000000c2 <SetPWM>:
  c2:	88 23       	and	r24, r24
  c4:	11 f4       	brne	.+4      	; 0xca
  c6:	6c bf       	out	0x3c, r22	; 60
  c8:	08 95       	ret
  ca:	81 30       	cpi	r24, 0x01	; 1
  cc:	09 f0       	breq	.+2      	; 0xd0
  ce:	08 95       	ret
  d0:	63 bd       	out	0x23, r22	; 35
  d2:	08 95       	ret
  d4:	08 95       	ret

000000d6 <SetSpeed>:
  d6:	cf 93       	push	r28
  d8:	df 93       	push	r29
  da:	ec 01       	movw	r28, r24
  dc:	18 16       	cp	r1, r24
  de:	19 06       	cpc	r1, r25
  e0:	2c f4       	brge	.+10     	; 0xec
  e2:	81 e0       	ldi	r24, 0x01	; 1
  e4:	0e 94 56 00 	call	0xac
  e8:	6c 2f       	mov	r22, r28
  ea:	06 c0       	rjmp	.+12     	; 0xf8
  ec:	80 e0       	ldi	r24, 0x00	; 0
  ee:	0e 94 56 00 	call	0xac
  f2:	8c 2f       	mov	r24, r28
  f4:	81 95       	neg	r24
  f6:	68 2f       	mov	r22, r24
  f8:	80 e0       	ldi	r24, 0x00	; 0
  fa:	0e 94 61 00 	call	0xc2
  fe:	df 91       	pop	r29
 100:	cf 91       	pop	r28
 102:	08 95       	ret

00000104 <main>:
 104:	cf e5       	ldi	r28, 0x5F	; 95
 106:	d8 e0       	ldi	r29, 0x08	; 8
 108:	de bf       	out	0x3e, r29	; 62
 10a:	cd bf       	out	0x3d, r28	; 61
 10c:	1a ba       	out	0x1a, r1	; 26
 10e:	89 e0       	ldi	r24, 0x09	; 9
 110:	87 bb       	out	0x17, r24	; 23
 112:	14 ba       	out	0x14, r1	; 20
 114:	80 e8       	ldi	r24, 0x80	; 128
 116:	81 bb       	out	0x11, r24	; 17
 118:	0e 94 47 00 	call	0x8e
 11c:	0e 94 4d 00 	call	0x9a
 120:	78 94       	sei
 122:	80 91 71 00 	lds	r24, 0x0071
 126:	90 91 72 00 	lds	r25, 0x0072
 12a:	aa 27       	eor	r26, r26
 12c:	97 fd       	sbrc	r25, 7
 12e:	a0 95       	com	r26
 130:	ba 2f       	mov	r27, r26
 132:	8f 3f       	cpi	r24, 0xFF	; 255
 134:	91 05       	cpc	r25, r1
 136:	a1 05       	cpc	r26, r1
 138:	b1 05       	cpc	r27, r1
 13a:	29 f0       	breq	.+10     	; 0x146
 13c:	24 f0       	brlt	.+8      	; 0x146
 13e:	8f ef       	ldi	r24, 0xFF	; 255
 140:	90 e0       	ldi	r25, 0x00	; 0
 142:	a0 e0       	ldi	r26, 0x00	; 0
 144:	b0 e0       	ldi	r27, 0x00	; 0
 146:	81 30       	cpi	r24, 0x01	; 1
 148:	2f ef       	ldi	r18, 0xFF	; 255
 14a:	92 07       	cpc	r25, r18
 14c:	2f ef       	ldi	r18, 0xFF	; 255
 14e:	a2 07       	cpc	r26, r18
 150:	2f ef       	ldi	r18, 0xFF	; 255
 152:	b2 07       	cpc	r27, r18
 154:	24 f4       	brge	.+8      	; 0x15e
 156:	81 e0       	ldi	r24, 0x01	; 1
 158:	9f ef       	ldi	r25, 0xFF	; 255
 15a:	af ef       	ldi	r26, 0xFF	; 255
 15c:	bf ef       	ldi	r27, 0xFF	; 255
 15e:	0e 94 6b 00 	call	0xd6
 162:	df cf       	rjmp	.-66     	; 0x122

00000164 <_SetSpeed>:
 164:	cf 93       	push	r28
 166:	df 93       	push	r29
 168:	ec 01       	movw	r28, r24
 16a:	18 16       	cp	r1, r24
 16c:	19 06       	cpc	r1, r25
 16e:	54 f4       	brge	.+20     	; 0x184
 170:	60 e0       	ldi	r22, 0x00	; 0
 172:	86 2f       	mov	r24, r22
 174:	0e 94 61 00 	call	0xc2
 178:	81 e0       	ldi	r24, 0x01	; 1
 17a:	0e 94 56 00 	call	0xac
 17e:	6c 2f       	mov	r22, r28
 180:	81 e0       	ldi	r24, 0x01	; 1
 182:	0b c0       	rjmp	.+22     	; 0x19a
 184:	60 e0       	ldi	r22, 0x00	; 0
 186:	81 e0       	ldi	r24, 0x01	; 1
 188:	0e 94 61 00 	call	0xc2
 18c:	80 e0       	ldi	r24, 0x00	; 0
 18e:	0e 94 56 00 	call	0xac
 192:	8c 2f       	mov	r24, r28
 194:	81 95       	neg	r24
 196:	68 2f       	mov	r22, r24
 198:	80 e0       	ldi	r24, 0x00	; 0
 19a:	0e 94 61 00 	call	0xc2
 19e:	df 91       	pop	r29
 1a0:	cf 91       	pop	r28
 1a2:	08 95       	ret

000001a4 <updatePos>:
}
 

 
SIGNAL (SIG_INTERRUPT0) {  // fix this signal name!!! INT0
	updatePos();
}
 
SIGNAL (SIG_INTERRUPT1) { // fix this signal name!!! INT1
	updatePos();
}
 
void updatePos() {
/*	get the bits        PIND     = XXXXiiXX
  	clear space       & 0x0C     = 0000ii00
  	or in old status  | oldstate = XX00iijj
 	clean up          & 0x0F     = 0000iijj  */  
	oldstate = oldstate | (PIND & 0x0C); // Update Oldstate 
 1a4:	40 b3       	in	r20, 0x10	; 16
 1a6:	4c 70       	andi	r20, 0x0C	; 12
 1a8:	80 91 70 00 	lds	r24, 0x0070
 1ac:	48 2b       	or	r20, r24
	position += offsets[oldstate]; 	     // Update Position
 1ae:	e0 e6       	ldi	r30, 0x60	; 96
 1b0:	f0 e0       	ldi	r31, 0x00	; 0
 1b2:	e4 0f       	add	r30, r20
 1b4:	f1 1d       	adc	r31, r1
 1b6:	80 81       	ld	r24, Z
 1b8:	99 27       	eor	r25, r25
 1ba:	87 fd       	sbrc	r24, 7
 1bc:	90 95       	com	r25
 1be:	20 91 71 00 	lds	r18, 0x0071
 1c2:	30 91 72 00 	lds	r19, 0x0072
 1c6:	82 0f       	add	r24, r18
 1c8:	93 1f       	adc	r25, r19
 1ca:	90 93 72 00 	sts	0x0072, r25
 1ce:	80 93 71 00 	sts	0x0071, r24
	oldstate = oldstate >> 2; 
 1d2:	46 95       	lsr	r20
 1d4:	46 95       	lsr	r20
 1d6:	40 93 70 00 	sts	0x0070, r20
 1da:	08 95       	ret

000001dc <__vector_1>:
 1dc:	1f 92       	push	r1
 1de:	0f 92       	push	r0
 1e0:	0f b6       	in	r0, 0x3f	; 63
 1e2:	0f 92       	push	r0
 1e4:	11 24       	eor	r1, r1
 1e6:	2f 93       	push	r18
 1e8:	3f 93       	push	r19
 1ea:	4f 93       	push	r20
 1ec:	5f 93       	push	r21
 1ee:	6f 93       	push	r22
 1f0:	7f 93       	push	r23
 1f2:	8f 93       	push	r24
 1f4:	9f 93       	push	r25
 1f6:	af 93       	push	r26
 1f8:	bf 93       	push	r27
 1fa:	ef 93       	push	r30
 1fc:	ff 93       	push	r31
 1fe:	0e 94 d2 00 	call	0x1a4
 202:	ff 91       	pop	r31
 204:	ef 91       	pop	r30
 206:	bf 91       	pop	r27
 208:	af 91       	pop	r26
 20a:	9f 91       	pop	r25
 20c:	8f 91       	pop	r24
 20e:	7f 91       	pop	r23
 210:	6f 91       	pop	r22
 212:	5f 91       	pop	r21
 214:	4f 91       	pop	r20
 216:	3f 91       	pop	r19
 218:	2f 91       	pop	r18
 21a:	0f 90       	pop	r0
 21c:	0f be       	out	0x3f, r0	; 63
 21e:	0f 90       	pop	r0
 220:	1f 90       	pop	r1
 222:	18 95       	reti

00000224 <__vector_2>:
 224:	1f 92       	push	r1
 226:	0f 92       	push	r0
 228:	0f b6       	in	r0, 0x3f	; 63
 22a:	0f 92       	push	r0
 22c:	11 24       	eor	r1, r1
 22e:	2f 93       	push	r18
 230:	3f 93       	push	r19
 232:	4f 93       	push	r20
 234:	5f 93       	push	r21
 236:	6f 93       	push	r22
 238:	7f 93       	push	r23
 23a:	8f 93       	push	r24
 23c:	9f 93       	push	r25
 23e:	af 93       	push	r26
 240:	bf 93       	push	r27
 242:	ef 93       	push	r30
 244:	ff 93       	push	r31
 246:	0e 94 d2 00 	call	0x1a4
 24a:	ff 91       	pop	r31
 24c:	ef 91       	pop	r30
 24e:	bf 91       	pop	r27
 250:	af 91       	pop	r26
 252:	9f 91       	pop	r25
 254:	8f 91       	pop	r24
 256:	7f 91       	pop	r23
 258:	6f 91       	pop	r22
 25a:	5f 91       	pop	r21
 25c:	4f 91       	pop	r20
 25e:	3f 91       	pop	r19
 260:	2f 91       	pop	r18
 262:	0f 90       	pop	r0
 264:	0f be       	out	0x3f, r0	; 63
 266:	0f 90       	pop	r0
 268:	1f 90       	pop	r1
 26a:	18 95       	reti
